Old Version of VLSI System Design

The information on this page refers to academic year 2003-2004 and is no longer valid for the current version of the course.
Only in exceptional cases, students will be allowed to do the old version of the course on an individual basis (no lectures, self study and project). Please contact Sabih Gerez prior to starting.
The description of the examination, which consists of practical projects and an oral session with the lecturer, is still valid for students that have followed the course in the academic year 2003-2004 or earlier.

Compulsory Material

The material to be studied for this course consists of:

The book:

Wolf, W., "Modern VLSI Design, System-on-Chip Design, Third Edition", Prentice Hall PTR, Upper Saddle River, New Jersey, (2002). Note: If you have the second edition, you don't need to buy the third.	The author's site contains the transparencies developed by him and other valuable information.
	Amazon UK
	Amazon US

The handout VHDL for Simulation and Synthesis (Version 2: January 19, 2004).
The slides of the lectures (see below).

Slides

The slides updated for the academic year 2003-2004 have a release date later than December 2003. In addition, the date is displayed on a red background. It is the intention to update the list of slides after each lecture.

Topic Corresponding Book Chapter Main author(s) Release Date

Organization - Sabih Gerez December 8, 2003

Introduction to VLSI Design Chapter 1 Wayne Wolf (*) December 3, 2002 (@)

Transistors and Layout Chapter 2 Wayne Wolf (*) December 8, 2003

Logic Gates, Delay and Power Chapter 3 Wayne Wolf (*) December 21, 2003

Combinational Logic: Critical Path, Crosstalk, Power Chapter 4 Wayne Wolf (*) January 12, 2004

Sequential Logic: Latches, Flipflops, Two-Phase Clocking Chapter 5 Wayne Wolf (*) January 12, 2004

Testing: Fault models, Test-Pattern Generation and Scan Parts of Chapters 4, 5, 7 and 10 Wayne Wolf (*) January 19, 2004

VHDL Synthesis Survey None Sabih Gerez June 25, 2001 (@)(+)

Subsystem Design: Pipelining, Shifters, Adders, ALUs, Multipliers Most of Chapter 6 Wayne Wolf (*) Feburary 16, 2004

Subsystem Design: Memories Last part of Chapter 6 Wayne Wolf (*) February 29, 2004

Register-Level and High-Level Synthesis Chapter 8 Wayne Wolf (*) March 3, 2004

High-Level Transformations None Sabih Gerez March 3, 2003 (@)

Low-Power Design None Sabih Gerez June 25, 2001 (@)

Layout Design: Floorplanning, Routing, Packaging Chapter 7 Wayne Wolf (*) February 25, 2003 (++)

Design Methodology Chapter 9 Wayne Wolf (*) February 18, 2002 (++)

Various CAD Tools Chapter 10 Wayne Wolf (*) February 25, 2002 (++)

(*) Slides slightly modified with permission of the author. Pages marked with an ocre University of Twente logo are written by Sabih Gerez for material covered by the book and those marked with a blue logo for material not covered by the book.
(@) Material not updated for acacemic year 2003-2004.
(+) The full source of information on the topic is the handout on VHDL simulation and synthesis (see above).
(++) Material not presented in the academic year 2003-2004 and not part of the examination.

Examination and Projects

The course has a study load of 100 hours. 40 of these are reserved for attending the lectures and studying the book. 60 are spent on a project. The project can be performed by an individual student or a team of two students. The results of this project combined with a short oral examination on the project and theory determine the mark for the course.

Oral Examination

The oral examination starts with a discussion on the project. The theory part of the oral examination will cover all compulsory material as mentioned above.

The goal of the examination is to verify whether the student has sufficient knowledge of the part of theory not covered by the project. There will be questions on general concepts, not on details.

The final mark for the course is the mark for the project increased or decreased by at most one depending on the performance on the theoretical part of the oral examination.

When the project has been performed by a team of two students, both participants are expected to attend the oral examinaiton simultaneously and to be able to defend all aspects of the project. They take turns in answering the questions. Depending on the defense, it may happen that the project mark is not the same for both.

Project

User accounts and passwords for the projects can be obtained from our secretary Anneke van Essen. Teams of two persons share one account. The same account is used for all projects.

The following projects are available for the academic year 2003-2004.

Project Description Study Load

VHD Introduction to VHDL and VHDL Simulation 2-4 hours

SYN Introduction to VHDL Synthesis 4-8 hours

ADD Adder Synthesis and Characterization 8-12 hours

SEC 2nd-Order IIR Filter Implementation rest

You are encouraged to propose an alternative design for Project SEC; contact me (Sabih Gerez) to obtain an approval for your proposal before starting to work on it.

Topic	Corresponding Book Chapter	Main author(s)	Release Date
Organization	-	Sabih Gerez	December 8, 2003
Introduction to VLSI Design	Chapter 1	Wayne Wolf (*)	December 3, 2002 (@)
Transistors and Layout	Chapter 2	Wayne Wolf (*)	December 8, 2003
Logic Gates, Delay and Power	Chapter 3	Wayne Wolf (*)	December 21, 2003
Combinational Logic: Critical Path, Crosstalk, Power	Chapter 4	Wayne Wolf (*)	January 12, 2004
Sequential Logic: Latches, Flipflops, Two-Phase Clocking	Chapter 5	Wayne Wolf (*)	January 12, 2004
Testing: Fault models, Test-Pattern Generation and Scan	Parts of Chapters 4, 5, 7 and 10	Wayne Wolf (*)	January 19, 2004
VHDL Synthesis Survey	None	Sabih Gerez	June 25, 2001 (@)(+)
Subsystem Design: Pipelining, Shifters, Adders, ALUs, Multipliers	Most of Chapter 6	Wayne Wolf (*)	Feburary 16, 2004
Subsystem Design: Memories	Last part of Chapter 6	Wayne Wolf (*)	February 29, 2004
Register-Level and High-Level Synthesis	Chapter 8	Wayne Wolf (*)	March 3, 2004
High-Level Transformations	None	Sabih Gerez	March 3, 2003 (@)
Low-Power Design	None	Sabih Gerez	June 25, 2001 (@)
Layout Design: Floorplanning, Routing, Packaging	Chapter 7	Wayne Wolf (*)	February 25, 2003 (++)
Design Methodology	Chapter 9	Wayne Wolf (*)	February 18, 2002 (++)
Various CAD Tools	Chapter 10	Wayne Wolf (*)	February 25, 2002 (++)

Project	Description	Study Load
VHD	Introduction to VHDL and VHDL Simulation	2-4 hours
SYN	Introduction to VHDL Synthesis	4-8 hours
ADD	Adder Synthesis and Characterization	8-12 hours
SEC	2nd-Order IIR Filter Implementation	rest
You are encouraged to propose an alternative design for Project SEC; contact me (Sabih Gerez) to obtain an approval for your proposal before starting to work on it.